| 摘要 |
1292783 F.E.T. logic Circuits NATIONAL CASH REGISTER CO 19 April 1971 [19 March 1970] 22399/71 Heading H3T [Also in Division G4] An integrated circuit includes two serialparallel converters the serial inputs to which are connected to respective circuit input terminals, and logical circuitry having a number of parallel inputs connected to respective parallel outputs of the serialparallel converters and a number of parallel outputs connected to the respective parallel inputs of a parallel-serial converter, the serial output of which is connected to a circuit output t erminal. By forming the converters as a part of the integrated circuit the number of data terminals is reduced to three. General.-The converters may be shift registers formed from two or four phase I.G.F.E.T. circuits, the clock pulses being supplied through additional terminals or being, at least in part, internally generated. In an embodiment only two shift registers are provided, one serving both as a serial-parallel and a parallel-serial converter. As described each operation cycle is delineated by n x 4 overlapping shift pulses (#1s-#4s), where n is the number of stages in the shift register, followed by four logic clock pulses (#1L-Q4L), the shift pulses serving to shift in new data and shift out processed data. In the illustrated embodiment two input shift registers 40, 42, a series of logic stages 46a-46n, and an output shift register 44 are provided. Circuit details.-Each four phase shift register - stage, e.g. stage 48a consists of two four phase circuits 50a, 52a each comprising three transistors, 54, 56, 58. In operation and following the leading edges of #1s and #2s, transistors 54 and 56 conduct causing a negative voltage to appear on line 66 and the stray capacitance 72 to charge negatively. Following the trailing edge of #1s, #2s remains negative and transistor 54 switches off, 56 remaining on. If the input data bit is "1" transistor 58 conducts as capacitor 70 is negatively charged, capacitor 72 discharges via transistors 56 and 58 (since #1s=OV and the source of transistor 58= OV), and the output on line 66=OV, i.e. a "0" bit. Similarly if the input data bit is a "0", the output date bit is a "I". Stage 52a is exactly similar apart from the phase of its clock pulses #3s, #4s. Thus at the end of a cycle #1s-#4s a data bit at the gate of transistor 58 at the input to stage 48a is transferred to line 68 and is stored on the gate capacitance of the input transistor of stage 48b. Five more similar sequences load six data bits into the two identical input shift registers 40, 42. The parallel outputs of the two shift registers 78a-78n, 80a-80n are connected to respective inputs of a number of NOR gates 46a-46n. Each gate is similar to the shift register stages above using clock pulse #1L-#4L to perform a logical NOR on its two inputs. The gate outputs are connected to the gates of the respective input transistors, e.g. 108, in the output shift register 44 via switches, e.g. 96. With the output data stored in shift register 44 and fresh input data stored in registers 20, 28 a new sequence starts. The pulses #1s, #2s shift the data in registers 40, 42, 44 half a stage, and the pulses #3s, #4s cause the gate capacitance of the input transistors to each stage to assume the voltage of the output of the preceding stage so that as the old data is shifted out new data is shifted in. When the new data is loaded the logic clock pulses #1L- #4L occur, and so on. In a further embodiment, Fig. 3 (not shown), one shift register acts both as an input serialparallel converter and an output parallel to serial converter. In operation data is shifted into the registers and is applied in parallel to the logic units via switches which are rendered non- conductive during the logic portion of the sequence. The logic outputs are then passed to the input/output register via a further set of switches and replace the old input data. As fresh input data is serially shifted in the output data is serially shifted out. |
