| 摘要 |
PURPOSE:To simplify the constitution, by increasing or reducing the number of frequency dividing pulses in accordance with the phase difference between a data signal RD and a timing signal RT and by generating increasing and reducing pulses by two D type flip flops (D-FF) and one J-K flip flop (J-KFF). CONSTITUTION:The output of a phase comparing circuit at the time when the phase of RD advances more than that of RT is applied to a terminal 14, and the output of the phase comparing circujit at the time when the phase of RD lags more than that of RT is applied to a terminal 15. Signals of terminals 14 and 15 stored in D-FFs 2A and 2B are transferred to a J-KFF 2C by the clock pulse inputted to a terminal 16. The output of the J-KFF 2C is gated in gate circuits 2D and 2E by the clock pulse. Outputs of gate circuits 2D and 2E are used as reset timing of D-FFs 2A and 2B. The number of frequency dividing pulses is increased by one in an outut 17 when the signal is applied to the terminal 14, and the number of frequency dividing pulses is decreased by one in the output 17 when the signal is applied to the terminal 15. |
