| 摘要 |
<p>PURPOSE:To restore the normal receiving state immediately even if false acquisition occurs in the receiving side, by setting one data of transmission frames to all ''1''s. CONSTITUTION:A data generating source 1 generates a start signal ST, 8-bit data, and a stop signal SP. ST and SP are inputted to a parallel-series converter 3 directly, and data is inputted to the converter through OR gates 2(1)...2(8). A counter 4 counts data from the start of the first frame to the end of the second frame by the data transmission start signal from the data generating source 1 and supplies a start signal to a fixed data generating source 5. The fixed data generating source 5 generates 8-bit data of all ''1''s as the third frame. The ST of the first frame is received erroneously as ''1'', and ''0'' in data of the first frame is received as the ST bit, and thus, false acquisition occurs. Meanwhile, since data of the third frame is all ''1''s, the normal receiving state is restored by the ST of the fourth frame.</p> |
