| 摘要 |
PURPOSE:To elevate the degree of integration, by connecting FETs in series between an electric power source and an output, connecting the same number of same conductive FETs in parallel between ground and the output, and applying complementary signals to the gates of corresponding FETs. CONSTITUTION:N channel (CH)FETsQ1-Q5 are connected in series between a circuit electric power source line VDD and an output line OUT, NCHFETsQ6-Q10 are connected in parallel between the output line and a ground line, and inverters I1-I5 are provided so that complementary signals S1-S5 and -S1--S5 are applied to the corresponding Q1 and Q6, Q2 and Q7, Q3 and Q8, Q4 and Q9, and Q5 and Q10, respectively. In this way, since a DC path is not generated in the circuit, the power consumption is reduced, and also a multiinput NOR gate circuit which is small-sized and high in speed is obtained. Furthermore, since it is unnecessary to form P-well, its occupied area is reduced to half of that of a PCH type FET, and its high integration is executed. |
