| 摘要 |
PURPOSE:To reduce the irregularity in response time without reducing the scanning time, by synchronizing the scanning in resetting the scan pulse generation counter when the synchronization demand signal is inputted. CONSTITUTION:A counter 3 allows a CPU 2 to set the count value. Each time a clock comes, the count value reduces by one. When the count value reaches 0, a scan interruption pulse is generated and the set point is reset. The CPU 2 repeats an input processing, an arithmetic processing and an output processing when the scan interruption signal is generated. On the other hand, when the data set is inputted from outside, the counter 3 is initialized and the set point is reset. In this way, the operation time can be shortened without reducing the operation quantity and the irregularity in response time can thus be reduced. |
