| 摘要 |
<p>Configurations of Boolean elements for implementing a sequential GF(2n) Galois multiplication gate are disclosed. Each configuration includes a single subfield GF(2m) Galois multiplication gate, where m is a positive integral divisor of n, e.g., n = 8 and m = 2, and assorted controls. Also disclosed is a sequential implementation of a GF(2n) Galois linear module as described in the J. T. Ellison Patent No. 3,805,037 wherein the controls of the sequential GF(2n) multiply gate cause the Galois addition (bit-wise Exclusive-OR) of an n-bit binary vector, Z, to the final Galois product.</p> |
