| 摘要 |
A filter utilizing charge transfer devices for providing recursive transfer functions with a transmission zero at d.c. or zero frequency is described. The filter includes a circular charge transfer shift register having an even number N of stages, greater than two, and first, second, third and fourth linear charge transfer shift registers. All five shift registers are clocked at the same frequency. A first input sequence of packets of charge representing positive weight components of a signal, and a second sequence of packets of charge representing negative weight components of the signal are provided. Means are provided for dividing each of the packets of charge of the first input sequence into a first part and a second part and for applying each of the first parts of the packets of the first input sequence to the input stage of the first shift register and for applying each of the second parts of the packets of the first input sequence to the input stage of the second shift register. The charge packet in the first charge storage cell in the Kth stage of the first shift register is combined with the charge packet in the first charge storage cell of the Nth stage of the circular shift register. The combined packet of charge is divided into two portions, a first portion being stored in the first charge storage cell of the Kth stage of the first shift register from which it is clocked out and sensed and a second portion being stored in the first charge storage cell of the Nth stage of the circular shift register. The charge packet in the first charge storage cell of the Lth stage of the second shift register is combined with the charge packet in the Mth stage of the circular shift register, where M is an integer less than N/2 and L=K+M. Means are provided for dividing each of the packets of charge of the second input sequence into a first part and a second part and for applying each of the first parts of the packets of the second input sequence to the input stage of the third shift register and for applying each of the second parts of the packets of the second input sequence to the input stage of the fourth shift register. The charge packet in the first charge storage cell in the Kth stage of the third shift register is combined with the charge packet in the first charge storage cell of the (N/2)th stage of the circular shift register. The combined packet of charge is divided into two portions, a first portion being stored in the first charge storage cell of the Kth stage of the third shift register from which it is clocked out and sensed and a second portion being stored in the first charge storage cell of the (N/2)th stage of the circular shift register. The charge packet in the first charge storage cell of the Lth stage of the fourth shift register is combined with the charge packet in the (N/2+M)th stage of the circular shift register. A first output sequence of packets of charge representing the positive components of an output signal is obtained at the output of the first shift register. A second output sequence of packets of charge representing the negative components of the output signal is obtained at the output of the second shift register. The output signal is obtained by differentially summing corresponding charge packets in the first and second output sequences.
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