| 摘要 |
1,261,494. Semi-conductor devices. TOKYO SHIBAURA ELECTRIC CO. Ltd. 26 Feb., 1970 [27 Feb., 1969 (3); 28 Feb., 1969 (2); 23 May, 1969], No. 9346/70. Heading H1K. Carrier mobility in both channel regions of a pair of complementary field-effect transistors in a diamond-structure or zinc blend-structure semi-conductor body is maximized by arranging the channels to be mutually perpendicular and to lie in selected crystallographic axis relative to the plane of the major face of the body. If the major face lies in a plane in the [100] zone (i.e. with its normal perpendicular to the [100] axis) and has its normal within 0‹ and 45‹, 45‹ exclusive, of the [011] axis, the N-channel lies along the [100] axis while the P-channel lies perpendicular thereto. If, however, the major face lies in a plane in the [011] zone there are two possibilities. Firstly, if the normal to the face is within 0‹ and 35‹ 15' of the [011] axis, the N-channel and P-channel lie respectively perpendicular and parallel to the [011] axis. Secondly, if the normal to the face is 35‹ 16' to 90‹ from the [011] axis, 90‹ exclusive, the N-channel and P-channel lie respectively parallel and perpendicular to the [011] axis. Further limitations on the plane of the major surface may be dictated by the need to minimize the surface state density. Thus, for planes in the [011] zone, the angle between the normal to the face and the [011] axis preferably lies between 48‹ 46' and 84‹ 16' while for planes in the [100] zone the angle between the normal to the face and the [011] axis preferably lies between 6‹ and 37‹ 20'. Semiconductor materials to which the invention is applicable include Si, Ge, semi-conducting diamond, GaAs, GaP and GaSb. The fieldeffect transistors may be of the insulated-gate, junction-gate or Schottky-barrier-gate types, and in the first mentioned case the gate insulation may comprise phosphorus-doped SiO 2 to improve stability, and the channel lengths of the complementary devices may differ. Fig. 7 shows a NAND-gate including four P-channel MOSFETs 42-45 in which adjacent devices share common source and drain regions 51-53. The gate electrodes 57-60 of the devices 42-45 are common to the gates of four perpendicularly aligned N-channel MOSFETs 46-49 sharing common N+ source and drain regions 55, 56 in an N-type region 41.
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