| 摘要 |
PURPOSE:To digitize the system overall, by discriminating the duty factor of the output signal of a digital phase lock loop (DPLL) digitally and by inserting the duty factor linearly to obtain a demodulation data signal. CONSTITUTION:The duty factor of an output signal 10 of a DPLL5 is discriminated digitally by a digital discriminating circuit, and this duty factor is inserted linearly by a converting circuit 13 to obtain a demodulation data signal 8. That is, the zero crossing waveform of a binary frequency deviation modulation signal 9 is inputted to the DPLL5, and the output signal 10 is inputted to a digital discriminating circuit 12, and the duty factor of the output signal 10 is discriminated on a basis of a high- speed sample and its pulse count value. An output 14 is inputted to the converting circuit 13 and is not only converted to DC components but also inserted linearly. This output 11 is inputted to a discriminating circuit 7 to discriminate whether the output 11 is larger than a constant threshold or not, thereby outputting a demodulation data signal 8. |
