LSI Circuit logic structure including data compression circuitry

摘要

A logic structure for an LSI digital circuit includes data compression circuitry for deriving a signature word from the data on a multiplicity of internal nodes which are not directly accessible from the terminals of the circuit. The signature word provides error information concerning the data on the internal nodes which are not otherwise available for testing purposes. The addition of data compression circuitry facilitates the testing of LSI digital circuits and can be complemented with minimal overhead chip area.