发明名称 MOS TYPE SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To obtain an MOS device which has no erroneous operation and the stepwise disconnection of a wire by forming a field insulating layer consecutively integrally with a buried type insulation isolating layer. CONSTITUTION:A resist mask 9 is covered on an SiO2 film 2 on a P type Si substrate 1. When a CF4 plasma is emitted to the film, the film is then etched with NH4F to form a hole 10 having a flaw. The mask 9 is removed, an O2 ion injecting layer 11 is formed, the layer is treated at higher thabn 1,100 deg.C, and a wavy thin insulaing layer 2 made of a field insulating layer 2b consecutive to a buried insulating layer 2a is formed. Thereafter, a memory cell MC, a wiring diffused layer C, and MOS transistor Q are formed on the region surrounded by an insulating layer 1a. Since the minority carrier due to the operation of the Q does not flow to the MC, the erroneous operation can be prevented with no leakage due to the inversion of the field and the layer 2b can be reduced in thickness with this configuration, the surface of the substrate can be smoothened, and no stepwise disconnection of the wire occurs.
申请公布号 JPS5745947(A) 申请公布日期 1982.03.16
申请号 JP19800121894 申请日期 1980.09.03
申请人 TOKYO SHIBAURA DENKI KK 发明人 MORITA SHIGERU
分类号 H01L27/00;H01L21/02;H01L21/265;H01L21/266;H01L21/762;H01L27/12;H01L29/78 主分类号 H01L27/00
代理机构 代理人
主权项
地址