发明名称 METHOD OF PRODUCING INTEGRATED CIRCUIT
摘要 The package has at least two levels of conductive interconnected patterns (26, 50A, 50B). The insulation containing the metal filled via openings (36) between the different levels consists of a lower layer (30) of an electrically insulating organic polymer end an overlying oxygen plasma resistant inorganic insulating layer (23). <??>In the formation of the interconnection metallurgy inorganic insulating layer (23) prohibits overetching in producing the hole pattern in the organic insulating layer (42) laterally surrounding the conductive pattern (50A, 50B) in the next level. The entirety of the insulation between the levels is thus ensured.
申请公布号 JPS5745952(A) 申请公布日期 1982.03.16
申请号 JP19810103497 申请日期 1981.07.03
申请人 INTERN BUSINESS MACHINES CORP 发明人 JIYOSEFU SUKINAA ROGAN;JIYON RESUTAA MOUAA FUOOSU;ROORA BESU ROSUMAN;JIERARUDEIN KOGIN SHIYUWARUTSU;CHIYAARUZU RAMUBAATO SUTANDOREE
分类号 H01L21/3205;H01L21/48;H01L21/768;H01L23/522 主分类号 H01L21/3205
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