| 摘要 |
PURPOSE:To reduce the maximum access time to a register, by realizing a simultaneous execution of write/read processes and a refresh process to the register. CONSTITUTION:A memory request signal 2 supplied from outside reaches selection gates G1 and G2. If the request of that time is identical with a register request, the gate G2 is turned off since no memory cycle signal 7 is produced. Then the signal 2 passes through the gate G1, and a register start signal 3 is outputted and processed. Accordingly the signal 2 is not supplied to a priority deciding circuit 9 on the register request, and as a result both the signal 3 and a refresh selection signal 11 are outputted when a refresh request 10 is produced concurrently. Thus both the refresh and register processes are carried out in parallel. |
