| 摘要 |
PURPOSE:To produce a timing signal by a PLA only, by providing a feedback loop FBL between input and output of a programmable logic array. CONSTITUTION:A PLA4 consists of a binary coded decimal BCD output decimal counter 4a, a BCD-t0-7 segment decoder 4b, a data selector-4c and a feedback counter 4f. Clocks are generated with the counter 4f and an FBL5 by external wiring. The counter 4a is counted with the input of a data signal CK1 to be counted, the BCD output is converted into a 7-segment data through the decoder 4b and selected to the selector 4c, and the output data 4d drives the 7-segment display device 3. The counter 4f counts the produced clock and outputs the selection signal of the selector 4c and the digit data output 4e. Each counter is reset with an RESET signal. Thus, the self-running type timing generating circuit not requring the clock generating circuit can be obtained. |
