发明名称 DISSIDENCE CIRCUIT
摘要 PURPOSE:To detect the dissidence of a level in complementary relation surely, by constituting the circuit with two detection circuits which detect one signal only for input complementary signals respectively and two capacitors and a logical circuit. CONSTITUTION:Relays R1, R2 are respectively actuated with complementary signals, S1, S2 of a prescribed repetitive period. Through the operating contacts r1(1), R1(3), r2(2), r2(4) and restoring contacts r1(2), r1(4), r2(1), r2(3) of the relays R1, R2, detection circuits 1, 2 for the signal S1 and detection circuits 3, 4 for the signal S2 are constituted. When the signal S1 is at level 1, a capacitor C1 is charged via the circuit 1, and when the signal S2 is at level 1, the charge of the capacitor C1 is discharged through the circuit 3 and an output relay MR, and a capacitor C2 is charged via the circuit 4. When the next signal S1 is at level 1, the charge in the capacitor C2 is discharged via the circuit 2 and the relay MR. By setting the discharge time constant of the capacitors C1, C2 to a prescribed value, when the signals S1, S2 are in complementary relation, a current flows to the relay MR alternately to make the MR operative at all times.
申请公布号 JPS5745728(A) 申请公布日期 1982.03.15
申请号 JP19800120610 申请日期 1980.09.02
申请人 KIYOUSAN SEISAKUSHO:KK 发明人 YAMADA AKIFUMI;ENOMOTO TAKASHI
分类号 H03K19/007;H03K19/21 主分类号 H03K19/007
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