发明名称 DRIVING CIRCUIT FOR CAPACITIVE LOAD
摘要 PURPOSE:To obtain a driving circuit which is suitable for IC-implementation and provides low-speed driving operation, by using pnp transistors (TR) and npn TRs as thyristors. CONSTITUTION:When a clock pulse supplied to a clock pulse input terminal 12 is inverted from a low to a high potential state, an emitter current flows to the 2nd pnp TR24 and the 1st npn TR14 turns on. At this time, the 2nd npn TR23 turns off because its base potential is -VCE and +VCE, turning off the 1st pnp TR13. Similarly, when the clock pulse is inverted from the high to the low potential state, the 2nd npn TR23 turns on the 1st pnp TR13 and the 2nd pnp TR24 turns on the 1st npn TR14.
申请公布号 JPS5744332(A) 申请公布日期 1982.03.12
申请号 JP19800119092 申请日期 1980.08.29
申请人 SONY KK 发明人 NISHIMURA TOSHIJI;NOGUCHI TAKASHI
分类号 H03K17/66;H03K5/02 主分类号 H03K17/66
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