| 摘要 |
PURPOSE:To carry out the competition control for the internal and external request signals with use of no delaying circuit, by controlling the generation of the internal request signal of a refresh, etc. plus the memory start based on the internal request signal by means of a clock whose pulse width is freely controlled. CONSTITUTION:The internal request signal and the start signal of a refresh, etc. are generated via a flip-flop FF1, an NOR circuit NOR, an FF3 and an NAND circuit NAND through synchronizing with the front and rear edges of a pulse, whose width is freely controlled, povided from an oscillator OSC. While, in the time when the external request signal is preceded than the internal request signal which is applied to a competition control circuit, the write-in/readout cycle period signal RWCY is generated from a timing producing circuit in accordance with the write-in/readout start signal provided from an FF2. At the same time, the start signal of a refresh, etc. is inhibited during this period via the gate NAND to control the competition of the internal and external request signals. Accordingly the pulse width provided from the oscillator OSC is controlled in accodance with a period during which the write/ read starting signal is generated and then the signal RWCY is generated to eliminate a delaying circuit. |
