| 摘要 |
PURPOSE:To obtain correct result of operation in high speed, by making zero detection of the data in upper digits than the data digit number plus one digit of the 1st operand, to the 2nd operand after shift left for the number of digits exceeding the data digit number of the 1st operand. CONSTITUTION:The data length L1 of the 1st operand is stored in a counter 11, data length L2 of the 2nd operand is stored in a counter 12, and shift digit number N is stored in a counter 13. Through the shift operation to the 2nd operand, when the data for L1+1 digit's share is stored in a buffer register 18, if the upper priority digits of the 2nd operand which can not be stored in the register 18, the data of the upper priority digits of the 2nd operand are sequentially outputted from the 2nd operand register 17 via a multiplexer 19 and adder 21 to make zero check at a data check section 25. If not zero, it is taken as overflow and if zero, normal operation is made. |
