发明名称 Supervisory circuit for parallel connected inverters - provides sequence of connection and disconnection to assist system management
摘要 <p>The supervisory circuit comprises a number of logic arrays equal to the number of inverters which can be connected in parallel to the power supply or load. All the circuit cards are identical, and have the necessary terminals to permit interconnection between inverters. By the use of time delays, logic gates and a flip flop the required information is gathered. This data about which inverter was switched on first, and the number of inverters currently running in parallel. The complementary information indicating which inverter was sw tched off first can also be given. The circuit allow the management of the inverter system to share operating times between all units. As all cards are the same there is a saving in manufacturing effort.</p>
申请公布号 DE3030388(A1) 申请公布日期 1982.03.11
申请号 DE19803030388 申请日期 1980.08.12
申请人 LICENTIA PATENT-VERWALTUNGS-GMBH 发明人 VOELLMEKE,ERWIN,ING.
分类号 H02M1/00;H02M7/48;H02M7/493;(IPC1-7):02J3/38 主分类号 H02M1/00
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