| 摘要 |
PURPOSE:To enable normal operation even at a high clock frequency with a quick transfer by reducing the transition period in the transfer of the charge to an output section from a final transfer electrode. CONSTITUTION:An insulation film 22 is applied on a p type Si substrate 21 and transfer electrodes 211-233, an output gate electrode 24 and a reset electrode 25 while a terminal 261 is connected to the electrodes 231 and 233 to apply a clock pulse phi1 and terminal 262 is to the electrode 232 to apply a clock pulse phi2. p<+> Type regions 271-273 are separately provided at parts of the substrate 21 positioned in part below the electrodes 231-233 to give the directivity in the charge transfer by generating an asymmetrical potential. An n<+> type floating region 28 is formed at a part of the substrate 21 on the side adjacent to an output gate electrode 24 of the electrode 25 or an n<+> type reset drain region 29 on the opposite side thereof. A source follower circuit 30 comprising a power source, an MOS type transistor 31 and load resistances 32 and 33 are connected to the region 28 and the power source is directly connected to the region 29. |
