摘要 |
A high speed parallel digital adder includes a control circuit which is the subject of this invention. The control circuit is a single integrated circuit having: add/subtract select logic for selecting the addition and subtraction functions of the adder; a one's complement carry look ahead logic unit for generating carry look ahead signals; and a logic unit for generating the sign of the resultant of the two operands, a complement data output, the underflow, and the overflow.
|