| 摘要 |
PURPOSE:To stabilize the operation, by inverting the polarity of input clock signal when the phase of operation start control is within a prescribed phase range, in a frequency division circuit possible for control of operation/stop with a control signal. CONSTITUTION:A reference signal from a reference oscillator 15 is inputted to a frequency divider 16 to form a reset signal (b), and the reset signal (b) causes phase variance to a clock signal (a) to invert the polarity of the clock (a), when the trailing edge of the clock signal (a) is included within the variable range of the trailing edge. Thus, even if phase variation is given to the reset signal (b), no phase jump is produced for the output of the frequency divider. |
