发明名称 CENTRAL ARITHMETIC PROCESSOR
摘要 PURPOSE:To decrease the total number of instructions, by installing a decoder selection register that sotres the value showing the decoder circuit group to be selected. CONSTITUTION:Instruction decoder circuit groups 61-6n are installed along with a decoder selection register 10 and a selected register decoder 11. Thus outputs b1- bn of the groups 61-6n are prepared for an instruction code, and the control signals can be produced to execute (n) units of different instructions.
申请公布号 JPS5741741(A) 申请公布日期 1982.03.09
申请号 JP19800118080 申请日期 1980.08.26
申请人 NIPPON DENKI KK 发明人 YASUDA SADAHIRO
分类号 G06F9/30;G06F9/318;G06F9/40 主分类号 G06F9/30
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