| 摘要 |
PURPOSE:To realize sharing for both the logic and edge directions of an input signal caused by the difference of the system specifications, by securing the setting of those two directions for every spot and by a program. CONSTITUTION:An input signal supplied from a process P is converted in terms of signal through an interface circuit IF and then drives a differentiating circuit SS through a logic converting circuit CV. A flip-flop ISR is set by the signal of the circuit SS, and an input of interruption to a CPU is transmitted. An edge direction setting register circuit FR can be set freely from the CPU, and the circuit CV gives an inversion or no inversion to the logic of signal according to the state of the circuit FR. Thus the edge can be detected with either of the rise or fall of the input signal to be transmitted to the CPU. |
