| 摘要 |
PURPOSE:To reduce the rate of error production for data reproduction through a small jitter, by providing a buffer at a lead/lag phase controlling circuit and delaying the time point of judgement of lead/lag. CONSTITUTION:A buffer memory MM4 is provided in a lead/lag position controlling circuit and lead/lag information is inputted to an up-down counter ctr. Only when the lead comes to specified l bits due to the consecution of the value, it can be judged as over-lead, and only when the delay in l bits comes, it can be judged as delay signal to delay the time point of judgement of lead/lag. Thus, the jitter produced in a pickup clock at data reproduction can be reduced. |
