| 摘要 |
PURPOSE:To obtain the fine and highly accurate pattern by attaching a pattern forming material on a substrate having a eaves shape or a nearly vertical step, and performing etching from the vertical direction. CONSTITUTION:An Si3N4 2 is provided on a P type Si substrate 1 and SiO2 3 is layered. A mask whose etching speed is slower than that of the film 3 is layered on the film 3, and the film 3 is selectively etched. Furthermore the side of the film 3 is etched. Then the end face of the film 3 becomes nearly vertical. After the coating with polycrystalline Si 4, reactive sputter etching is performed with CF4+O2 gas, and polycrystalline Si 5 is left on the end face of the SiO2 3. Then, the SiO2 3 is selectively etched by HF solution, and fine polycrystallike Si pattern 5 is obtained. The width of the pattern is approximately equal to the thickness of polycrystalline Si 4. The pattern is ormed with the accuracy (about 0.01mum) within the thickness control range in a CVD method. The Si3N4 2 is etched by the remaining mask 5, and N<+> layers 6 and 7 are formed. Then an FET with a fine gate width is completed without using a resist. |
