发明名称 CODE ERROR CORRECTING CIRCUIT
摘要 PURPOSE:To raise the efficiency of transmission of a data, by constituting so that the same frame is transmitted only once in case when a code error rate in trnsmitting a data is low, and the same frame is transmitted three times continuously in case when its code error rate is high. CONSTITUTION:A CPU8 decides whether a code error rate in case of transmitting a data is good or not, from a data of a result of check by a CRC circuit 7, and S/N in the data transmission line, etc. For instance, now, the CPU8 decides that the code error rate is low, and sets a mode so that 1 frame is transmitted only once. In this case, logic on a conductor 81 is inverted, and as a result, a switching circuit 9 outputs an output signal of a frame synchronization detecting circuit 1, and a gate circuit 10 outputs only a data part of a signal on a conductor 11, which is controlled by an output of the frame synchronization detecting circuit 1, and inputs it to a data buffer 6. On the other hand, in case when the code error rate is high, the CPU8 makes the logic on the conductor 81 different from said case, and sets it to a three continuous transmissions using shift registers 2a-3b and a deciding circuit 4.
申请公布号 JPS5741050(A) 申请公布日期 1982.03.06
申请号 JP19800116606 申请日期 1980.08.22
申请人 MITSUBISHI DENKI KK 发明人 HARADA NAGAYASU
分类号 H04L1/08;(IPC1-7):04L1/08 主分类号 H04L1/08
代理机构 代理人
主权项
地址