| 摘要 |
PURPOSE:To make the circuit suitable for error check in the transmission of serial data, by detecting the specific bit pattern sequence having specific bit arrangement out of the serial data received from an external circuit and inverting the polarity of only the serial data of a fixed number received immediately before the apttern sequence to output it. CONSTITUTION:An input signal is serially inputted to a shift register 2 and the parallel output terminal of the first half 2a is connected to a gate means 4. When the specific bit pattern sequence is inpputted, it is detected at the gate means 4, and FF6 is at on-state and a counter 5 is started. Then, since the output of the FF6 is at high level, the serial data of the latter half 2b of the shift register 2 is inputted to an exclusive logical sum gate 3 and each bit is inverted. When the counter 5 counts the number of bits of the latter half 2b of the shift register 2, the FF6 is reset and the serial data is not inverted thereafter and outputted as it is. |
