| 摘要 |
A semiconductor orthogonal memory system in which a grid of row and column chip select conductors, and a grid of row and column data conductors, are coupled to an array of memory modules. Common address bits are extended to all modules. The memory is several (eight, in the illustrative embodiment) times faster than the processor with which it operates, and accordingly three of the address bits are cycled during each read or write processor operation. This results in a sequence of eight bits on each row or column data conductor; the number of utilizable bit storage locations in each module is thus increased by a factor of 64. Each module can include several chips, each of which may be divided into multiple segments. In the case of two chips, and two segments per chip, the same number segment in the same number chip in all modules of the selected row or column of modules can be identified by doubling the number of chip select conductors otherwise required and by utilizing one of the address bits to distinguish between the two segments on each chip. This technique increases the number of utilizable bit storage locations in each module to 256. The overall arrangement allows the number of bits in an orthogonal word to be significantly greater than the number of bits in a normal word, without requiring wire linking of the entire bit-storage array and without requiring the array as a whole to be dimensioned to match the entire orthogonal memory.
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