| 摘要 |
PURPOSE:To output a clock for control which is delayed in phase behind a shift clock to a 1st inverter and to simplify a logic and circuit scale by inputting the output of the 1st clocked inverter which shifts and outputs data in synchronism with the shift clock to a 2nd clocked inverter. CONSTITUTION:Inverters 1 and 3 among 1st clocked inverters 1-4 of a shift register circuit are brought under output control with a shift clock phi1 and the inverters 2 and 4 are brought under output control with a shift clock phi2. The clocks phi1 and phi2 are inverted in phase shifting by a half cycle and respective data outputs are inputted to 2nd corresponding clocked inverters 5-8. The inverters 5 and 7 among the inverters 5-8 are brought under output control with a control clock phi1' and the inverters 6 and 8 are brought under output control with a control clock phi2'. Then those control are generated by ANDing the clocks phi1 and phi2 with delayed signals of those clocks phi1 and phi2. |
