| 摘要 |
PURPOSE:To obtain an FET with a high withstand voltage eliminating increase in the area of the elements by providing an n layer across two p layers on an n type substrate while a Schottky electrode provided on the n layer over the p layer. CONSTITUTION:P layers 12 are provided on an n<-> type Si substrate 11 at a given space and n<+> layers 13 are made on the respective p layers. An n layer 14 is formed on the surface of the substrate 11 adjacent to the facing surface of the layers 13 across the layers 12. Covered with SiO215, the layers are etched and a Schottkey electrode 16 is made therein over a P layer 13 to make a first gate G1. A metal electrode 17 is provided and the electrode on the n<+> layer 13 is made a source S while the electrode of the p layers 12 as second gate G2. A metal electrode 18 is provided on the back of the substrate to make a drain D. This provides a cascode connection type FET which comprises a Schottky gate type FET1 including the layer 13-G1-G2- the layer 14 and a junction type FET2 having an n<-> layer grasped by the p layers 12 as channel and the electrode 18 as drain. The larger thickness of the substrate 11 gives a higher withstand voltage thereby eliminating increase in the area. |
