| 摘要 |
PURPOSE:To obtain a clock signal having a shift of 1/2 period or double period of an external clock signal, by constituting an internal FF circuit so that it works at the front or rear edge or with both the front and rear edges of the external clock signal. CONSTITUTION:When q control input signal 14 is logic 0, an internal clock signal 16, i.e., the output of an exclusive logical circuit 11 has the same phase as an external clock signal. Accordingly, an FF12 within a chip works at the front edge of a signal 15 when it is viewed from the outside of the chip. In case the signal 14 is fixed at logic 0, the polarity is inverted between the signals 15 and 16 by the nature of the circuit 11. Accordingly, the circuit 12 works at the rear edge of the signal 15 when it is viewed from the outside of the chip. This is equivalent to the fact that a clock delayed by 1/2 period is supplied. In case a clock signal delayed by a certain time is supplied in the form of the signal 14, the circuit 12 works at the front and rear edges of the signal 15 when it is viewed from the outside of the chip. This is equivalent to the supply of a clock having double frequency. |
