| 摘要 |
PURPOSE:To improve application efficiency of the main storage section and to improve the performance of the whole information processing equipment, by reducing the number of memory access when the boundary location of operand data in a main storage section is not specified. CONSTITUTION:A memory address register 101 and a data alignment circuit 102 are installed in a CPU100, and a memory array 201 is installed in a main storage section 200. Memory blocks 201U and 201L are installed in the array 201, and a memory address bus 301 from the register 101 of the CPU100 is connected to address registers 202U and 202L, each of which is connected to each block 201U and 201L, respectively. Also, a data bus 302 from the CPU200 is connected to writing data registers 203U and 203L, each of which is connected to each block 201U and 201L, respectively, and then connected further to reading data RDU and RDL. Then, the application efficiency of the memory section 200 is improved, by reducing the number of access when the boundary location of operand data in the memory section 200 is not specified. |
