发明名称 DEETADENSOSOCHI
摘要 PURPOSE:To reduce responsibility of the CPU without installing any devices to perform priority transmission separately, by reading out data of the memory of the computer with a direct memory access device and giving the data to a cyclic data transmitting device. CONSTITUTION:A transmitting data address generator 13 which successively generates addresses in a main memory 12 of data to be transmitted to a computer 1, is installed, and a priority transfer of data transmission is performed by adding 1 to the contents of the generator 13 every time when data in the memory 12 are read out by one word. Moreover, when the CPU11 requests to preferentially transmit specific data, outputs from these memories 12 and 14 and generator 13 are given to a direct memory access device 2 after the address is added to a priority transmission data address memory 14 which sets the address, and data from the computer 1 is transmitted to a cyclic data transmitting device 3 at the transmitting side by the device 2. Then, the data is delivered to another cyclic data transmitting device 4 at the receiving side by the transmitting device 3, and thus transmission of data is simplified.
申请公布号 JPS5736338(A) 申请公布日期 1982.02.27
申请号 JP19800110138 申请日期 1980.08.11
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 SATO HIROO
分类号 H04J3/24;G06F13/00;G06F13/28;H04L5/22;H04L29/10;H04Q9/00 主分类号 H04J3/24
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