发明名称 DEISUKUSEIGYOSOCHI
摘要 PURPOSE:To simultaneously perform data transfer processing of the disk equipment and the system bus so that the processing time is reduced and correction of data errors is easily made, by dividing a sector buffer which can read and write randomly, into two lines, each of which can store information for one sector. CONSTITUTION:To the internal bus of a disk controlling equipment, a processor 19 which controls data transfer and an error correcting code analyzing circuit 20 are connected, and sector buffers 11 and 12 which can read and write randomly, are connected to the bus. Moreover, a buffer changeover circuit 17 which changes over the control of buffers 11 and 12 at an interval which is equal to the sector processing time, is connected to each buffer 11 and 12, and the buffers 11 and 12 are alternately used based on the output of the circuit 17. The data transfer processing of one sector analyzed at the circuit 20 is synchronized to the data transfer processing between the buffer 12 and the system bus, while the transferred data from the disk equipment are successively stored in the buffer 11, and, when an error is detected, the error is corrected by the analysis information.
申请公布号 JPS5736355(A) 申请公布日期 1982.02.27
申请号 JP19800110695 申请日期 1980.08.12
申请人 NIPPON ELECTRIC CO 发明人 YATSUSE OSAMI
分类号 G06F3/06;G06F13/00 主分类号 G06F3/06
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