| 摘要 |
An asynchronous multi-stable state circuit particularly adapted for use in a shift register. The bits move through the stages asynchronously. Each stage is capable of storing a 1, 0 or phi bit and has three control states; quiescent, set and clear. When a given stage is in the quiescent state a clear signal from a succeeding stage will cause the given stage to store or register a bit phi therein. This effectively puts the stage in a waiting condition. When this occurs, the control state switches from quiescent to set. When in the set state, the data 0 or 1 from the preceding stage is entered into the given stage for storage therein. Next, the given stage switches to the clear state and sends a clear signal to put the preceding stage in the waiting condition, i.e., storage of phi . When the preceding stage stores a bit phi , it sends a signal back to the given stage to switch the given stage to the quiescent state. |
