发明名称 DOUBLE PERIOD PULSE GENERATING CIRCUIT
摘要 PURPOSE:To make the duty of an output pulse of a frequency doubler to about 50%, by making direct current for output pulses of the frequency doubler and applying it to a variable delay circuit. CONSTITUTION:An input pulse f1 and an output pulse f1d of a variable delay circuit 1 are applied to an exclusive logical sum circuit EX to obtain a double frequency pulse f2. The logical product between the pulses f2 and f1 is taken out from a gate G and smoothed at a smoothing circuit 2. A DC voltage in which the duty of the input pulse f2 from the gate G is taken out from a voltage comparison circuir A, the resistance of an FETQ is varied with this voltage to change the delay time, resulting that the duty of the pulse f2 is at almost 50%.
申请公布号 JPS5735415(A) 申请公布日期 1982.02.26
申请号 JP19800110195 申请日期 1980.08.13
申请人 HITACHI LTD 发明人 OOSAKI MASASHIGE;KIHARA TOSHIMASA
分类号 H03K3/64;H03K5/00;(IPC1-7):03K3/64 主分类号 H03K3/64
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