| 摘要 |
PURPOSE:To improve the gate sensitivity of the subject thyristor without reducing dV/dt resistant strength by a method wherein, in the case of a three-terminal element having four-layer structure, an n layer (or a p layer) is provided, aparting from an emitter layer, on the p base layer (or an n base layer) on which a gate electrode will be provided. CONSTITUTION:For example, in the case of a four-layer thyristor consisting of a pE layer, an nB layer, a pB layer and an nE layer, an nO layer 5 is formed in the pB layer 2 simultaneously with the diffusion performed on the nE layer 4, for example, and the nO layer and the pB layer are short-circuited by an electrode G. In this structure, when the gate voltage having the gate G as positive and a cathode as negative is applied, a junction 13 is biased inversely and the gate current reaches the nE layer 4 through the route as shown by solid arrow lines, thereby enabling to increase the implanting efficiency and increase the gate sensitivity. On the other hand, the dV/dt resistant strength is not reduced even when the nO layer is provided, because the direction of the displacement current ingredient shown by the dotted lines has no relation with the existence of the nO layer 5. Accordingly, a thyristor which is suited to a high-sensitive and low current capacity element having a low gate trigger current can be obtained. |
