| 摘要 |
PURPOSE:To discriminate and regenerate an NRZ code signal, by extracting a timing component form a receiving NRZ encoding signal, and making it a latch signal as a clock. CONSTITUTION:An NRZ encoding signal of a transmission speed f0, which has been inputted is differentiated by a differentiating circuit 1, and it is made a reset signal of a counter 5. The counter 5 counts a clock signal of 2Nf1(f1 f0) from an oscillator 4, and is operated as a 2N-scale counter which is carried at every 3N. An OR gate 7 generates a clock of an FF8 by a carry signal and an output of a logical gate 6, compares phase of an output of the FF8 and an output which has divided by an FF12 an output of VCO for outputting a clock signal of F0Hz, by a comparing circuit 9, and generates a control signal of VCO. A receiving NRZ signal from a delaying circuit 3 is inputted to a latching circuit 2, and when an output of the VCO11 is made to a clock, this NRZ signal is discriminated and regenerated with high reliability. |
