发明名称 Error detecting and correcting RAM assembly
摘要 A RAM assembly, or card, includes a random access memory portion for the data bits, as well as a random access memory portion for corresponding check bits. The card includes a parity generator and a parity comparator to determine the presence of an error. There is also included a decoder to decode the output of the comparator to determine the nature and position of the error. The error is not only corrected in the transmission to the central processor but is also fed back to correct the error in the RAM itself. Thus the errors that would appear in the RAM do not accumulate.
申请公布号 US4317201(A) 申请公布日期 1982.02.23
申请号 US19800136262 申请日期 1980.04.01
申请人 HONEYWELL, INC. 发明人 SEDALIS, PATRICK A.
分类号 G06F11/10;G06F11/267;G06F12/16;(IPC1-7):G06F11/10 主分类号 G06F11/10
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