发明名称 MEMORY TESTING SYSTEM
摘要 PURPOSE:To perform a test for a memory including an address system test with a low cost, by dividing a memory into >=2pts. and supplying the same address signal from the adress selecting circuits corresponding to each of the divided two memories. CONSTITUTION:Address distributing parts 5 and 6 correspond to 4-bit memories 1-0 and 1-1 obtained by dividing an 8-bit memory into two parts, and the same address data ADD1 or ADDn is supplied to the parts 5 and 6 respectively. The upper 4 bits and the lower 4 bits of an 8-bit writing data WD are written into the designated addresses of the memories 1-0 and 1-1 respectively. At the same time, a check bit formed after being supplied to a parity generating circuit 3 is written into an area 17. The data RD read out of the memories 1-0 and 1-1 are transmitted to a parity checking circuit 19 to check wheter the correct writing and reading is carried out for the data.
申请公布号 JPS5733497(A) 申请公布日期 1982.02.23
申请号 JP19800107196 申请日期 1980.08.06
申请人 FUJITSU LTD 发明人 ISHIKAWA HIROSHI;KOUNO HISAO
分类号 G06F12/16;G06F11/10;G11C29/08 主分类号 G06F12/16
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