发明名称 BUFFER MEMORY CONTROL SYSTEM
摘要 PURPOSE:To realize a high-speed MOVE instruction that satisfies the specific conditions, by obtaining no coincidence of contents between a main memory and a buffer. CONSTITUTION:A MOVE instruction orders that the data designated by an address A for instance is transferred to the region designated by an address B by an extent of length L. Both the fetch address A and the store address B given from a CPU and set to registers 3 and 4 exist at a tag part 10 of a buffer memory. In such case, a normal process is carried out. In case no address A exists at the part 10, a read request and the address A are sent to a main memory. At the same time, the address A is compared 9 with the address B. On the other hand, the result obtained by subtracting 15 the register 3 from the length L is compared 16 with the length of a line. As a result, the data read out of the address A of a main memory is written into the address B or an idle set.
申请公布号 JPS5733476(A) 申请公布日期 1982.02.23
申请号 JP19800105551 申请日期 1980.07.31
申请人 FUJITSU LTD 发明人 ITOU MATAO
分类号 G06F9/30;G06F12/08 主分类号 G06F9/30
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