| 摘要 |
PURPOSE:To greatly shorten a processing time for transferring a data, by providing a common memory circuit between control parts, and transferring the data as a block. CONSTITUTION:In case when data is transferred to a subcontrol part SP3 from a main control part MP1, at first the MP1 writes the data and an execution indicating condition of the SP3 in a communication memory circuit CM4, and after that, turns on a select signal 12. When the signal 12 is turned on, the SP3 turns off a ready signal 13, and sends back a response to the MP1. Subsequently, the CM4 is changed over to an address space of the SP3, interprets the contents of the CM4, which have been written by the MP1, and outputs the data to an output apparatus and processes it. In case when data is transferred to the MP1 from the SP3, the MP1 writes an input command, a data length, etc. in the CM4, and after that, the SP3 interprets the command. Subsequently, the SP3 writes the data in the CM4 from an input apparatus. The MP1 processes the data in the CM4 after confirming that this writing has ended. |
