| 摘要 |
PURPOSE:To control with less idle time by providing a bank controlling part that controls access in common against a pipeline device and by specifying timing with which the pipeline device accesses a vector register. CONSTITUTION:Element data are stored in a plurality of vector registers #0VR- #nVR so that said data are dispersed in an interleaved plurality bank units 1-0- 1-7 and each element of the registers #0VR-#nVR is accessed by one pipeline operating part 5 or a plurality of them and a memory pipeline 2. A bank slot that indicates timing with which the operating part 5 and the line 2 access each of units 1-0-1-7 is controlled in a bank controlling part 7. Furhter, when the operating part 5 and the line 2 access the registes #0VR-#nVR, a bank slot signal for access is sent to the controlling part 7, and a response signal as to whether it is possible or not against the signal from the controlling part 7 is sent to the operating part 5 and the line 2, thereby specifying timing of access. |
