| 摘要 |
PURPOSE:To increase the compressing efficiency and realize a simple and high- speed hardware, by dividing the multi-value time series signal into blocks, changing each signal into an unequal length code, changing the value of the signal delivered most frequently into a run length code of unequal length, and at the same time using a parallel arithmetic type array converting circuit. CONSTITUTION:The multi-value time series signal is divided by a synchronous signal and through a timing control circuit 3 and applied to the 1st and 2nd coders 5 and 4. A code V obtained by changing the multi-value signal into an unequal length code plus a code showing the run length of the code V are obtained by the 1st coder 5; while a run length coded code R from the calue of the signal delivered most frequently plus a code showing the run length of the code R are obtained by the 2nd coder 4. The signals S and V plus the code R are multiplexed through a multiplexing circuit 6 to obtain a code S10, and then a signal S11 is obtained by multiplexing the codes showing the run length of each code. Then the display signal showing the number of effective bits plus a parallel bit data in which the ineffective bits ''x'' and ''0'' are eliminated and the order of bits are rearranged by the display signal are obtained through a parallel arithmetic type array code converting circuit 7. |
