发明名称 MEMORY ACCESS CONTROLLING SYSTEM
摘要 PURPOSE:To make a large guantity of data buffers unnecessary, to allow a hardware to be reduced and to simplify the operation by preforming a memory access according to a priority of an element data that each access means makes an access object. CONSTITUTION:Requirements sent successsively from access ports VPA-VPD of arithmetic devices are received with address ports 5-8, and the element number of access data of request pointers 1-4 are set in the ports 5-8. A prescribed bit of address information in the ports 5-8 is compared in a comparator 16 for bus conflict check, and the compared result is added to a priority controlling circuit 17. Further, the element number of the pointers 1-4 are inputted into the circuit 17, and priority is determined in the circuit 17. Further a corresponding busy to be accessed is checked in a decoder 13 for LS busy check, a busy state is set in a group of LS busy latches 27. Further priority of the element data is determined by the circuit 17 and the registers 18-25 are accessed.
申请公布号 JPS5731066(A) 申请公布日期 1982.02.19
申请号 JP19800105926 申请日期 1980.07.31
申请人 FUJITSU LTD 发明人 ITOU MIKIO;TAMURA HIROSHI;OKAMOTO TETSUO;UCHIDA KEIICHIROU
分类号 G06F12/00;G06F12/06;G06F13/18;G06F17/16 主分类号 G06F12/00
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