发明名称 CLOCK PHASE CONTROL CIRCUIT
摘要 PURPOSE:To execute a synchronization of plural pieces of LSIs by monitoring a phase of the respective operation clocks of N pieces of LSIs, based on the operation clock of one piece of LSI as a reference, controlling a supply clock to a tooth-omitted shaped, as for the LSI of a discrepancy phase, and holding for a prescribed period until its LSI is synchronized. CONSTITUTION:N+1 pieces of LSIs 20-2N bring an input clock 101 and supply clocks 1021-102N to frequency division in the inside, respectively, and execute a data processing. A clock phase control circuit 1 supplies the supply clock to all the LSIs 21-2N except one piece of LSI 20, through this circuit, and on the other hand, inputs all of an operation clock 103 and same 1041 - same 104N which are brought to frequency division and formed by all the LSIs 20-2N, to this circuit and monitors them, and controls the supply clocks 1021-102N to the LSIs 21-2N so that all the operation clocks 103, 1041-104N which are brought to frequency division to be formed into the same phase. In such a way, LSIs which can execute a prescribed data processing on the supplied clock by the operation clock which is applied independently with frequency division and has formed, can be synchronized plurality.
申请公布号 JPS63238612(A) 申请公布日期 1988.10.04
申请号 JP19870072809 申请日期 1987.03.26
申请人 NEC ENG LTD 发明人 ANDO MITSUGI
分类号 H03L7/00;G06F1/04;G06F1/10;H04L1/00 主分类号 H03L7/00
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