| 摘要 |
PURPOSE:To generate both codes of parity check and remainder by the quantity of hardware of the extent of an ordinary remainder code generating circuit or so, by generating a parity check code to a data of 4 bits, from a output of an remainder generation device and an output of a specific pattern. CONSTITUTION:Current mode logic 1-13 shows a logical gate, respectively. Logical gates 1, 2 generate the remainder in case when a numerical value of 2 bits consisting of bits ''0'', ''1'' has been divided by a numerical value 3. In this case, BiTO1, RESO, BiTO1, RES1 and BiTO1 and RES2 show a remainder code to a data consisting of bits ''0'', ''1'', and when the remainder is ''0'', BiTO1 and RESO are ''1'' and others are ''0'', and when the remainder is ''1'', BiTO1 and RES1 only are ''1'' and others ''0'', and in case of a numerical value 2, BiTO1 and RES2 only are ''1'' and others are ''0''. The constitution and operation of logical gates 3, 4 are all the same as those of the bit 1, 2 side. |
