| 摘要 |
PURPOSE:To perform simultaneously transmission-reception and interruption of two data for one instruction without executing two kinds of instruction in esch processor by using simultaneously a signal of a writing action or a reading action to memories as generation of an interrupting signal or a reset action. CONSTITUTION:When a processor 1 sends a data to a processor 3, a data for an address of an interuption signal 5 to a processor 2 in an address area of a common memory 4 is writted by the processor 1. Further simultaneously, an interruption signal generating circuit 8 for the processor 2 inputs an address of a common bus 3 and decodes, and a signal 5 for the processor 2 is made to be active, thus the interruption is generated. Still more, memory contents of an address assingned to the signal 5 to the processor of itself in the memory 3 are read with the processor 2, and they are received as data. And simultaneously, the address is decoded in the circuit 8, an interruption of the processor 2 is reset, each of the processors 1, 2 performs simultaneously an interruption and data transmission-reception with one instruction. |
