发明名称 TIME-DIVISION MEMORY SYSTEM
摘要 PURPOSE:To decrease the number of memories, and to simplify the control over transmission and reception which reducing the price of a channel device, by using part of a channel memory, included in the time-division switch of a digital switchboard, for no-channel data. CONSTITUTION:Data transferred from a multiplexer 2 in a circuit correspondence part 1 to a highway 4, having 15-frame multiframe constitution by assigning 120 channels of channel signals and 8 channels of no-channel signals to one frame, are transmitted over 120 channels each of the channel and no-channel signals. Each memory cycle of the channel memory 9 of a time-division switch 8 consists of four steps of sequential writing, random reading, no-channel data reading, and random reading. According to outputs of counters 11 and 21, data are written by being specified by an address selector and channel data read out by the address RRA of a holding memory are transferred to the next stage via a register 23. No-channel data are readout by a signal controller 14 and transferred to the device 14.
申请公布号 JPS5730489(A) 申请公布日期 1982.02.18
申请号 JP19800104336 申请日期 1980.07.31
申请人 FUJITSU LTD 发明人 SUTANI YOSHIAKI;KOUNO HISAO
分类号 H04Q3/52;H04Q11/04 主分类号 H04Q3/52
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